INTENCLR

Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.

Name:: INTENCLR
Offset:: 0x04 [ID-0000067a]
Reset:: 0x00
Access:: PAC Write-Protection

Bit7	6	5	4	3	2	1	0
							EW
Access							R/W
Reset							0

Bit 0 – EW: Early Warning Interrupt Enable

Early Warning Interrupt Enable

Writing a '0' to this bit has no effect. 

Writing a '1' to this bit clears the Early Warning Interrupt Enable bit, which disables the Early Warning interrupt.

Value	Description
0	The Early Warning interrupt is disabled.
1	The Early Warning interrupt is enabled.