Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name:
INTENCLR
Offset:
0x04 [ID-00000a2f]
Reset:
0x00
Access:
PAC Write-Protection
Bit76543210
PLRDY
AccessR/W
Reset0

Bit 0 – PLRDY: Performance Level Interrupt Enable

Performance Level Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Performance Ready Interrupt Enable bit and the corresponding interrupt request.

ValueDescription
0 The Performance Ready interrupt is disabled.
1 The Performance Ready interrupt is enabled and will generate an interrupt request when the Performance Ready Interrupt Flag is set.