Cortex M0+ Configuration

Table 1. Cortex M0+ Configuration in Atmel SAM L21
Features Cortex M0+ options Atmel SAM L21 configuration
Interrupts External interrupts 0-32 29
Data endianness Little-endian or big-endian Little-endian
SysTick timer Present or absent Present
Number of watchpoint comparators 0, 1, 2 2
Number of breakpoint comparators 0, 1, 2, 3, 4 4
Halting debug support Present or absent Present
Multiplier Fast or small Fast (single cycle)
Single-cycle I/O port Present or absent Present
Wake-up interrupt controller Supported or not supported Not supported
Vector Table Offset Register Present or absent Present
Unprivileged/Privileged support Present or absent Absent - All software run in privileged mode only
Memory Protection Unit Not present or 8-region Not present
Reset all registers Present or absent Absent
Instruction fetch width 16-bit only or mostly 32-bit 32-bit

The ARM Cortex-M0+ core has two bus interfaces: