By default, the LUT output is a combinatorial function of the LUT inputs. This may cause some short glitches when the inputs change value. These glitches can be removed by clocking through filters, if demanded by application needs.
The Filter Selection bits in LUT Control register
(LUTCTRLx.FILTSEL) define the synchronizer or digital filter options. When a filter is
enabled, the OUT output will be delayed by two to five GCLK cycles. One APB clock after the
corresponding LUT is disabled, all internal filter logic is cleared.
Note: Events used as LUT input will also be
filtered, if the filter is enabled.
Figure 1. Filter
