The USB on-chip buffers comply with the Universal Serial
Bus (USB) v2.0 standard. All AC parameters related to these buffers can be found within
the USB 2.0 electrical specifications.
The USB interface is USB-IF certified :
- TID 40001709 - Peripheral Silicon
> Low/Full Speed > Silicon Building Blocks
- TID 120000459 - Embedded Hosts
> Full Speed
Electrical configuration required to be USB-compliant:
- the performance level must be PL2
only
- the CPU fequency must be higher
8MHz when USB is active (No contrain for USB suspend mode)
- the operating voltages must be
3.3V (Min. 3.0V, Max. 3.6V).
- the GCLK_USB frequency accuracy
source must be less than:
- in USB device mode, 48MHz
+/-0.25%
- in USB host mode, 48MHz
+/-0.05%
Table 1. GCLK_USB
Clock Setup Recommendations
| Clock
setup |
USB Device |
USB Host |
| DFLL48M |
Open loop |
No |
No |
| Close loop, Ref. internal OSC
source |
No |
No |
| Close loop, Ref. external XOSC
source |
Yes |
No |
| Close loop, Ref. SOF (USB
recovery mode)(1) |
Yes(2) |
N/A |
| FDPLL |
internal OSC (32K, 8M…) |
No |
No |
| external OSC (<1MHz) |
Yes |
No |
| external OSC (>1MHz) |
Yes(3) |
Yes |
Note:
- 1.When using DFLL48M in USB
recovery mode, the Fine Step value must be Ah to guarantee a USB clock at
+/-0.25% before 11ms after a resume. Only usable in LDO regulator mode.
- 2.Very high signal quality and crystal less. It is the best setup for USB Device
mode.
- 3.FDPLL lock time is short when the clock frequency source is high (> 1 MHz).
Thus, FDPLL and external OSC can be stopped during USB suspend mode to reduce
consumption and guarantee a USB wakeup time (See TDRSMDN in USB
specification).