Device Summary
Table 1. General Device Registers
Offset |
Name |
Bit Pos. |
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0x04 |
Reserved |
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0x05 |
Reserved |
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0x06 |
Reserved |
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0x07 |
Reserved |
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0x08 |
CTRLB |
7:0 |
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NREPLY |
SPDCONF[1:0] |
UPRSM |
DETACH |
0x09 |
15:8 |
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|
LPMHDSK[1:0] |
GNAK |
|
0x0A |
DADD |
|
ADDEN |
DADD[6:0] |
0x0B |
Reserved |
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0x0C |
STATUS |
7:0 |
LINESTATE[1:0] |
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SPEED[1:0] |
|
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0x0E |
Reserved |
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0x0F |
Reserved |
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0x10 |
FNUM |
7:0 |
FNUM[4:0] |
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0x11 |
15:8 |
FNCERR |
|
FNUM[10:5] |
0x12 |
Reserved |
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0x14 |
INTENCLR |
7:0 |
RAMACER |
UPRSM |
EORSM |
WAKEUP |
EORST |
SOF |
|
SUSPEND |
0x15 |
15:8 |
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LPMSUSP |
LPMNYET |
0x16 |
Reserved |
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0x17 |
Reserved |
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0x18 |
INTENSET |
7:0 |
RAMACER |
UPRSM |
EORSM |
WAKEUP |
EORST |
SOF |
|
SUSPEND |
0x19 |
15:8 |
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LPMSUSP |
LPMNYET |
0x1A |
Reserved |
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0x1B |
Reserved |
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0x1C |
INTFLAG |
7:0 |
RAMACER |
UPRSM |
EORSM |
WAKEUP |
EORST |
SOF |
|
SUSPEND |
0x1D |
15:8 |
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LPMSUSP |
LPMNYET |
0x1E |
Reserved |
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0x1F |
Reserved |
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0x20 |
EPINTSMRY |
7:0 |
EPINT[7:0] |
0x21 |
15:8 |
EPINT[15:8] |
0x22 |
Reserved |
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0x23 |
Reserved |
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Table 2. Device Endpoint Register n
Offset |
Name |
Bit Pos. |
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0x1m0 |
EPCFGn |
7:0 |
|
EPTYPE1[1:0] |
|
EPTYPE0[1:0] |
0x1m1 |
Reserved |
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0x1m2 |
Reserved |
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0x1m3 |
Reserved |
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0x1m4 |
EPSTATUSCLRn |
7:0 |
BK1RDY |
BK0RDY |
STALLRQ1 |
STALLRQ0 |
|
CURBK |
DTGLIN |
DTGLOUT |
0x1m5 |
EPSTATUSSETn |
7:0 |
BK1RDY |
BK0RDY |
STALLRQ1 |
STALLRQ0 |
|
CURBK |
DTGLIN |
DTGLOUT |
0x1m6 |
EPSTATUSn |
7:0 |
BK1RDY |
BK0RDY |
STALLRQ1 |
STALLRQ0 |
|
CURBK |
DTGLIN |
DTGLOUT |
0x1m7 |
EPINTFLAGn |
7:0 |
|
STALL1 |
STALL0 |
RXSTP |
TRFAIL1 |
TRFAIL0 |
TRCPT1 |
TRCPT0 |
0x1m8 |
EPINTENCLRn |
7:0 |
|
STALL1 |
STALL0 |
RXSTP |
TRFAIL1 |
TRFAIL0 |
TRCPT1 |
TRCPT0 |
0x1m9 |
EPINTENSETn |
7:0 |
|
STALL1 |
STALL0 |
RXSTP |
TRFAIL1 |
TRFAIL0 |
TRCPT1 |
TRCPT0 |
0x1mA |
Reserved |
|
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0x1mB |
Reserved |
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Table 3. Device Endpoint n Descriptor Bank 0
Offset 0x n0 + index |
Name |
Bit Pos. |
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0x00 |
ADDR |
7:0 |
ADD[7:0] |
0x01 |
15:8 |
ADD[15:8] |
0x02 |
23:16 |
ADD[23:16] |
0x03 |
31:24 |
ADD[31:24] |
0x04 |
PCKSIZE |
7:0 |
BYTE_COUNT[7:0] |
0x05 |
15:8 |
MULTI_PACKET_SIZE[1:0] |
BYTE_COUNT[13:8] |
0x06 |
23:16 |
MULTI_PACKET_SIZE[9:2] |
0x07 |
31:24 |
AUTO_ZLP |
SIZE[2:0] |
MULTI_PACKET_SIZE[13:10] |
0x08 |
EXTREG |
7:0 |
VARIABLE[3:0] |
SUBPID[3:0] |
0x09 |
15:8 |
|
VARIABLE[10:4] |
0x0A |
STATUS_BK |
7:0 |
|
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|
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|
ERRORFLOW |
CRCERR |
0x0B |
Reserved |
7:0 |
|
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|
0x0C |
Reserved |
7:0 |
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0x0D |
Reserved |
7:0 |
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0x0E |
Reserved |
7:0 |
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0x0F |
Reserved |
7:0 |
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Table 4. Device Endpoint n Descriptor Bank 1
Offset 0x n0 + 0x10 + index
|
Name |
Bit Pos. |
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|
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|
|
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0x00 |
ADDR |
7:0 |
ADD[7:0] |
0x01 |
15:8 |
ADD[15:8] |
0x02 |
23:16 |
ADD[23:16] |
0x03 |
31:24 |
ADD[31:24] |
0x04 |
PCKSIZE |
7:0 |
BYTE_COUNT[7:0] |
0x05 |
15:8 |
MULTI_PACKET_SIZE[1:0] |
BYTE_COUNT[13:8] |
0x06 |
23:16 |
MULTI_PACKET_SIZE[9:2] |
0x07 |
31:24 |
AUTO_ZLP |
SIZE[2:0] |
MULTI_PACKET_SIZE[13:10] |
0x08 |
Reserved |
7:0 |
|
|
|
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|
0x09 |
Reserved |
15:8 |
|
|
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0x0A |
STATUS_BK |
7:0 |
|
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|
ERRORFLOW |
CRCERR |
0x0B |
Reserved |
7:0 |
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|
0x0C |
Reserved |
7:0 |
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0x0D |
Reserved |
7:0 |
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0x0E |
Reserved |
7:0 |
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0x0F |
Reserved |
7:0 |
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