Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name:
INTENSET
Offset:
0x05 [ID-00000a2f]
Reset:
0x00
Access:
PAC Write-Protection
Bit76543210
PLRDY
AccessR/W
Reset0

Bit 0 – PLRDY: Performance Level Ready Interrupt Enable

Performance Level Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Performance Ready Interrupt Enable bit and enable the Performance Ready interrupt.

ValueDescription
0 The Performance Ready interrupt is disabled.
1 The Performance Ready interrupt is enabled.