Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name:
INTENCLR
Offset:
0x04 [ID-00000bc7]
Reset:
0x00
Access:
PAC Write-Protection
Bit76543210
EMPTY1EMPTY0UNDERRUN1UNDERRUN0
AccessR/WR/WR/WR/W
Reset0000

Bit 3 – EMPTY1: Data Buffer 1 Empty Interrupt Enable

Data Buffer 1 Empty Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Data Buffer 1 Empty Interrupt Enable bit, which disables the Data Buffer 1 Empty interrupt.

ValueDescription
0 The Data Buffer 1 Empty interrupt is disabled.
1 The Data Buffer 1 Empty interrupt is enabled.

Bit 2 – EMPTY0: Data Buffer 0 Empty Interrupt Enable

Data Buffer 0 Empty Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Data Buffer 0 Empty Interrupt Enable bit, which disables the Data Buffer 0 Empty interrupt.

ValueDescription
0 The Data Buffer 0 Empty interrupt is disabled.
1 The Data Buffer 0 Empty interrupt is enabled.

Bit 1 – UNDERRUN1: Underrun Interrupt Enable for DAC1

Underrun Interrupt Enable for DAC1

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Data Buffer 1 Underrun Interrupt Enable bit, which disables the Data Buffer 1 Underrun interrupt.

ValueDescription
0 The Data Buffer 1 Underrun interrupt is disabled.
1 The Data Buffer 1 Underrun interrupt is enabled.

Bit 0 – UNDERRUN0: Underrun Interrupt Enable for DAC0

Underrun Interrupt Enable for DAC0

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Data Buffer 0 Underrun Interrupt Enable bit, which disables the Data Buffer 0 Underrun interrupt.

ValueDescription
0 The Data Buffer 0 Underrun interrupt is disabled.
1 The Data Buffer 0 Underrun interrupt is enabled.