Pending Channels
Bit31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
Access | |||||||
Reset | |||||||
Bit23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Access | |||||||
Reset | |||||||
Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PENDCHn[15:8] | |||||||
AccessR | R | R | R | R | R | R | R |
Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PENDCHn[7:0] | |||||||
AccessR | R | R | R | R | R | R | R |
Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Pending Channel n [n=15..0]
This bit is cleared when trigger execution defined by channel trigger action settings for DMA channel n is started, when a bus error for DMA channel n is detected or when DMA channel n is disabled. For details on trigger action settings, refer to CHCTRLB.TRIGACT.
This bit is set when a transfer is pending on DMA channel n.