The DPLLC is enabled by writing a '1' to the Enable bit in the DPLL Control A register (DPLLCTRLA.ENABLE). The DPLLC is disabled by writing a zero to this bit.
The DPLLSYNCBUSY.ENABLE is set when the DPLLCTRLA.ENABLE bit is modified. It is cleared when the DPLL output clock CK has sampled the bit at the high level after enabling the DPLL. When disabling the DPLL, DPLLSYNCBUSY.ENABLE is cleared when the output clock is no longer running.
The frequency of the DPLL output clock CK is stable when the module is enabled and when the Lock bit in the DPLL Status register is set (DPLLSTATUS.LOCK).
When the Lock Time bit field in the DPLL Control B register (DPLLCTRLB.LTIME) is non-zero, a user defined lock time is used to validate the lock operation. In this case the lock time is constant. If DPLLCTRLB.LTIME=0, the lock signal is linked with the status bit of the DPLL, and the lock time varies depending on the filter selection and the final target frequency.
When the Wake Up Fast bit (DPLLCTRLB.WUF) is set, the wake up fast mode is activated. In this mode the clock gating cell is enabled at the end of the startup time. At this time the final frequency is not stable, as it is still during the acquisition period, but it allows to save several milliseconds. After first acquisition, the Lock Bypass bit (DPLLCTRLB.LBYPASS) indicates if the lock signal is discarded from the control of the clock gater (CG) generating the output clock CLK_DPLL.
| WUF | LTIME | CLK_DPLL Behavior |
|---|---|---|
| 0 | 0 | Normal Mode: First Edge when lock is asserted |
| 0 | Not Equal To Zero | Lock Timer Timeout mode: First Edge when the timer down-counts to 0. |
| 1 | X | Wake Up Fast Mode: First Edge when CK is active (startup time) |
| LBYPASS | CLK_DPLL Behavior |
|---|---|
| 0 | Normal Mode: the CLK_DPLL is turned off when lock signal is low. |
| 1 | Lock Bypass Mode: the CLK_DPLL is always running, lock is irrelevant. |
