CoreSight ROM Table Entry 0
| Bit31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ADDOFF[19:12] | |||||||
| AccessR | R | R | R | R | R | R | R |
| Resetx | x | x | x | x | x | x | x |
| Bit23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ADDOFF[11:4] | |||||||
| AccessR | R | R | R | R | R | R | R |
| Resetx | x | x | x | x | x | x | x |
| Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADDOFF[3:0] | |||||||
| AccessR | R | R | R | ||||
| Resetx | x | x | x | ||||
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FMT | EPRES | ||||||
| Access | R | R | |||||
| Reset | 1 | x | |||||
Address Offset
The base address of the component, relative to the base address of this ROM table.
Format
Always reads as '1', indicating a 32-bit ROM table.
Entry Present
This bit indicates whether an entry is present at this location in the ROM table.
This bit is set at power-up if the device is not protected indicating that the entry is not present.
This bit is cleared at power-up if the device is not protected indicating that the entry is present.