The DAC Controller can generate the following output events:
- Data Buffer 0 Empty (EMPTY0): Generated
when the internal data buffer of DAC0 is empty. Refer to DMA Operation for details.
- Data
Buffer 1 Empty (EMPTY1): Generated when the internal data buffer of DAC1 is empty. Refer
to DMA Operation for details.
Writing a '1' to an Event Output bit in the
Event Control Register (EVCTRL.EMPTYEOx) enables the
corresponding output event. Writing a '0' to this bit disables the corresponding output
event. Refer to the Event System chapter for details on configuring the event system.
The DAC Controller can take the following actions on an input event:
- DAC0 Start Conversion (START0):
DATABUF0 value is transferred into DATA0 as soon as DAC0 is ready for the next
conversion, and then conversion is started. START0 is considered as asynchronous to
GCLK_DAC, thus it is resynchronized in the DAC Controller. Refer to Digital to Analog Conversion for details.
- DAC1
Start Conversion (START1): DATABUF1 value is transferred into DATA1 as soon as DAC1 is
ready for the next conversion, and then conversion is started. START1 is considered as
asynchronous to GCLK_DAC, thus it is resynchronized in the DAC Controller. Refer to
Digital to Analog Conversion for details.
Writing a '1' to an Event Input bit in the
Event Control register (EVCTRL.STARTEI
x) enables the
corresponding action on input event. Writing a '0' to this bit will disable the
corresponding action on input event.
Note: When several events are connected to the DAC Controller, the enabled action will be
taken on any of the incoming events. Refer to EVSYS – Event System for details on
configuring the event system.
By default, DAC Controller detects rising
edge events. Falling edge detection can be enabled by writing '1' to EVCTRL.INVEIx.