Device Interrupt Enable Clear
Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LPMSUSP | LPMNYET | ||||||
Access | R/W | R/W | |||||
Reset | 0 | 0 | |||||
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMACER | UPRSM | EORSM | WAKEUP | EORST | SOF | SUSPEND | |
AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset0 | 0 | 0 | 0 | 0 | 0 | 0 |
Link Power Management Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Link Power Management Suspend Interrupt Enable bit and disable the corresponding interrupt request.
Value | Description |
---|---|
0 | The Link Power Management Suspend interrupt is disabled. |
1 | The Link Power Management Suspend interrupt is enabled and an interrupt request will be generated when the Link Power Management Suspend interrupt Flag is set. |
Link Power Management Not Yet Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Link Power Management Not Yet interrupt Enable bit and disable the corresponding interrupt request.
Value | Description |
---|---|
0 | The Link Power Management Not Yet interrupt is disabled. |
1 | The Link Power Management Not Yet interrupt is enabled and an interrupt request will be generated when the Link Power Management Not Yet interrupt Flag is set. |
RAM Access Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding interrupt request.
Value | Description |
---|---|
0 | The RAM Access interrupt is disabled. |
1 | The RAM Access interrupt is enabled and an interrupt request will be generated when the RAM Access interrupt Flag is set. |
Upstream Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding interrupt request.
Value | Description |
---|---|
0 | The Upstream Resume interrupt is disabled. |
1 | The Upstream Resume interrupt is enabled and an interrupt request will be generated when the Upstream Resume interrupt Flag is set. |
End Of Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the End Of Resume interrupt Enable bit and disable the corresponding interrupt request.
Value | Description |
---|---|
0 | The End Of Resume interrupt is disabled. |
1 | The End Of Resume interrupt is enabled and an interrupt request will be generated when the End Of Resume interrupt Flag is set. |
Wake-Up Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt request.
Value | Description |
---|---|
0 | The Wake Up interrupt is disabled. |
1 | The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake Up interrupt Flag is set. |
End of Reset Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the End of Reset interrupt Enable bit and disable the corresponding interrupt request.
Value | Description |
---|---|
0 | The End of Reset interrupt is disabled. |
1 | The End of Reset interrupt is enabled and an interrupt request will be generated when the End of Reset interrupt Flag is set. |
Start-of-Frame Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Start-of-Frame interrupt Enable bit and disable the corresponding interrupt request.
Value | Description |
---|---|
0 | The Start-of-Frame interrupt is disabled. |
1 | The Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Start-of-Frame interrupt Flag is set. |
Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Suspend Interrupt Enable bit and disable the corresponding interrupt request.
Value | Description |
---|---|
0 | The Suspend interrupt is disabled. |
1 | The Suspend interrupt is enabled and an interrupt request will be generated when the Suspend interrupt Flag is set. |