The following registers are
enable-protected, meaning that they can only be written when the TC is disabled
(CTRLA.ENABLE =0):
- Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST)
bits
- Drive Control register (DRVCTRL)
- Wave register (WAVE)
- Event Control register (EVCTRL)
Enable-protected bits in the CTRLA register can be written at the same time as
CTRLA.ENABLE is written to '1', but not at the same time as CTRLA.ENABLE is written to '0'.
Enable-protection is denoted by the "Enable-Protected" property in the register
description.
Before enabling the TC, the peripheral must
be configured by the following steps:
- 1.Enable the TC bus clock
(CLK_TCx_APB).
- 2.Select 8-, 16- or 32-bit counter mode
via the TC Mode bit group in the Control A register (CTRLA.MODE). The default mode is
16-bit.
- 3.Select one wave generation operation in the Waveform Generation Operation bit group
in the WAVE register (WAVE.WAVEGEN).
- 4.If desired, the GCLK_TCx clock can be
prescaled via the Prescaler bit group in the Control A register (CTRLA.PRESCALER).
- If the prescaler is used, select a prescaler synchronization operation via the
Prescaler and Counter Synchronization bit group in the Control A register
(CTRLA.PRESYNC).
- 5.If desired, select one-shot operation
by writing a '1' to the One-Shot bit in the Control B Set register
(CTRLBSET.ONESHOT).
- 6.If desired, configure the counting
direction 'down' (starting from the TOP value) by writing a '1' to the Counter
Direction bit in the Control B register (CTRLBSET.DIR).
- 7.For capture operation, enable the
individual channels to capture in the Capture Channel x Enable bit group in the
Control A register (CTRLA.CAPTEN).
- 8.If desired, enable inversion of the
waveform output or IO pin input signal for individual channels via the Invert Enable
bit group in the Drive Control register (DRVCTRL.INVEN).