Figure 1. Clock
Distribution
The SAM L21 clock system
consists of:
- Clock sources, controlled by OSCCTRL and OSC32KCTRL
- A clock
source provides a time base that is used by other components, such as
Generic Clock Generators. Example clock sources are the internal 16MHz oscillator (OSC16M),
external crystal oscillator (XOSC) and the Digital Frequency Locked
Loop (DFLL48M).
- Generic Clock Controller (GCLK), which generates,
controls and distributes the asynchronous clock consisting of:
- Generic Clock Generators: These are
programmable prescalers that can use any of the system clock sources as a
time base. The Generic Clock Generator 0 generates the clock signal
GCLK_MAIN, which is used by the Power Manager and the Main Clock (MCLK)
module, which in turn generates synchronous clocks.
- Generic Clocks: These are clock signals
generated by Generic Clock Generators and output by the Peripheral Channels,
and serve as clocks for the peripherals of the system. Multiple instances of
a peripheral will typically have a separate Generic Clock for each instance.
Generic Clock 0 serves as the clock source for the DFLL48M clock input (when
multiplying another clock source).
- Main Clock
Controller (MCLK)
- The MCLK
generates and controls the synchronous clocks on the system. This includes
the CPU, bus clocks (APB, AHB) as well as the synchronous (to the CPU) user
interfaces of the peripherals. It contains clock masks that can turn on/off
the user interface of a peripheral as well as prescalers for the CPU and bus
clocks.
The next figure shows an example where SERCOM0 is
clocked by the DFLL48M in open loop mode. The DFLL48M is enabled, the Generic Clock
Generator 1 uses the DFLL48M as its clock source and feeds into Peripheral Channel
13. The Generic Clock
13, also called
GCLK_SERCOM0_CORE, is connected to SERCOM0. The SERCOM0 interface, clocked by
CLK_SERCOM0_APB, has been unmasked in the APBC Mask register in the MCLK.
Figure 2. Example
of SERCOM Clock