Acquiring the lowest power consumption of the device requires some specific settings of the GPIOs in relation to the connected peripherals. The table below describes the settings needed for the lowest possible power consumption. If not otherwise noted, all pins should disable all digital logic (DIR = 0, INEN = 0 and PULLEN = 0).
| SAM E54 pin | Signal | State | Description |
|---|---|---|---|
| PC21 | ETH RESET | Output low | The on-board Ethernet PHY KSZ8091 continuously generates a 50 MHz clock signal to PA14 on the SAM E54. When the KSZ8091 is in reset the clock signal is not generated and the power consumption of the SAM E54 is reduced. |