Edge-Triggered Hardware Limit Mode

In Hardware Limit mode, the timer can be reset by the TMRx_ers external signal before the timer reaches the period count. Three types of Resets are possible:

• Reset on rising or falling edge (MODE[4:0] = 00011)
• Reset on rising edge (MODE[4:0] = 00100)
• Reset on falling edge (MODE[4:0] = 00101)

When the timer is used in conjunction with the CCP in PWM mode then an early Reset shortens the period and restarts the PWM pulse after a two clock delay. Refer to Figure 1.

Figure 1. Edge-Triggered Hardware Limit Mode Timing Diagram 
(MODE = 00100)

Note:

1. 1.BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.