PFM Erase Sequence

The sequence of events for erasing a block of internal program memory is:

  1. 1.Set NVMADR to an address within the intended sector.
  2. 2.Set the NVMEN bit to enable NVM
  3. 3.Perform the unlock sequence as described the NVM Unlock Sequence section
  4. 4.Set the SECER bit

If the PFM address is write-protected, the SECER bit will be cleared and the erase operation will not take place, NVMERR is signaled in this scenario.

The operation erases the sector indicated by masking the LSbs of the current NVMADR.

While erasing PFM, CPU operation is suspended and it resumes when the operation is complete. Upon completion the SECER bit is cleared in hardware, the NVMIF is set and an interrupt will occur if the NVMIE bit is also set.

The holding register data are not affected by erase operations and NVMEN will remain unchanged.

Figure 1. PFM Sector Erase Flowchart

Erasing a Program Flash Memory block

; This sample sector erase routine assumes that the target address
; specified by CODE_ADDR_UPPER and CODE_ADDR_HIGH contain a value within
; the PFM address range of the device.

           MOVLW   CODE_ADDR_UPPER    ; load NVMADR with the base
           MOVWF   NVMADRU            ; address of the memory block
           MOVLW   CODE_ADDR_HIGH
           MOVWF   NVMADRH
ERASE_BLOCK:
           BSF     NVMCON0, NVMEN     ; enable Program Flash Memory
           BCF     INTCON, GIE        ; disable interrupts
Required   MOVLW   CCh                ; first unlock byte for erase
Sequence   MOVWF   NVMCON2            ; write CCh
           MOVLW   33h                ; second unlock byte for erase
           MOVWF   NVMCON2            ; write 33h
           BSF     NVMCON1, SECER     ; start erase (CPU stalls)
           BSF     INTCON, GIE        ; re-enable interrupts
           BCF     NVMCON0, NVMEN     ; disable writes to memory
Important:
  1. 1.If a write or erase operation is terminated by an unexpected event, NVMERR bit will be set which the user can check to decide whether a rewrite of the location(s) is needed.
  2. 2.NVMERR is set if SECER is written to ‘1’ while NVMADR points to a write-protected address.
  3. 3.NVMERR is set if SECER is written to ‘1’ while NVMADR points to an invalid address location ( Refer to the device memory map and NVM Organization Table).