Master mode reception (Figure 1) is enabled by programming the RCEN Receive Enable bit.
Important: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded.
The Baud Rate Generator begins counting and on each rollover, the
state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSPSR.
After the falling edge of the eighth clock all the following events occur:
- The receive enable flag is automatically cleared
- The contents of the SSPSR are loaded into the SSPxBUF
- The BF flag bit is set
- The SSPxIF flag bit is set
- The Baud Rate Generator is suspended from counting
- The SCL pin is held low
The MSSP is now in Idle state awaiting the next command. When the buffer is read by the
CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at
the end of reception by setting the Acknowledge Sequence Enable, ACKEN
bit.