Setting the AHEN bit enables
additional clock stretching and interrupt generation after the eighth falling edge of a
received matching address. Once a matching address has been clocked in, CKP is cleared and
the SSPxIF interrupt is set.
Figure 1 displays a standard waveform of a 7-bit address slave transmission with AHEN enabled.
- 1.Bus starts Idle.
- 2.Master sends Start condition; the S bit is
set; SSPxIF is set if interrupt on Start detect is enabled.
- 3.Master sends matching address with R/W bit set. After the eighth falling edge of the SCL line the CKP bit is cleared and SSPxIF interrupt is generated.
- 4.Slave software clears SSPxIF.
- 5.Slave software reads the ACKTIM, R/W and D/A bits to determine the source of the interrupt.
- 6.Slave reads the address value from the SSPxBUF register clearing the BF bit.
- 7.Slave software decides from this information if it wishes to
ACK or not ACK and sets the ACKDT bit
accordingly.
- 8.Slave sets the CKP bit releasing SCL.
- 9.Master clocks in the ACK value from the slave.
- 10.Slave hardware automatically clears the CKP bit and sets SSPxIF after the ACK if the R/W bit is set.
- 11.Slave software clears SSPxIF.
- 12.Slave loads value to transmit to the master into SSPxBUF setting the BF bit.
Important: SSPxBUF cannot be loaded until after the ACK.
- 13.Slave sets the CKP bit releasing the clock.
- 14.Master clocks out the data from the slave and sends an ACK value on the ninth SCL pulse.
- 15.Slave hardware copies the ACK value into the ACKSTAT
bit.
- 16.Steps 10-15 are repeated for each byte transmitted to the master from the slave.
- 17.If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and
end the communication.
Important: Master must send a
not ACK on the last byte to ensure
that the slave releases the SCL line to receive a Stop.
Figure 1. I2C
Slave, 7-bit Address, Transmission (AHEN = 1
)