Interrupt Flag Register - Normal Mode

The individual status bit can be cleared by writing a '1'e to its bit location. This allows each bit to be set without use of a read-modify-write operation on a single register.
Name:
INTFLAGS
Offset:
0x0B
Reset:
0x00
Access:
-
Bit76543210
CMP2CMP1CMP0OVF
AccessR/WR/WR/WR/W
Reset0000

Bit 6 – CMP2: Compare Channel 2 Interrupt Flag

Compare Channel 2 Interrupt Flag

See CMP0 flag description.

Bit 5 – CMP1: Compare Channel 1 Interrupt Flag

Compare Channel 1 Interrupt Flag

See CMP0 flag description.

Bit 4 – CMP0: Compare Channel 0 Interrupt Flag

Compare Channel 0 Interrupt Flag

The compare interrupt flag (CMPn) is set on a compare match on the corresponding compare channel.

For all modes of operation, the CMPn flag will be set when a compare match occurs between the count register (CNT) and the corresponding compare register (CMPn). The CMPn flag will not be cleared automatically and has to be cleared by software. This is done by writing a one to its bit location.

Bit 0 – OVF: Overflow/Underflow Interrupt Flag

Overflow/Underflow Interrupt Flag

This flag is set either on a TOP (overflow) or BOTTOM (underflow) condition, depending on the WGMODE setting. OVF is not automatically cleared and needs to be cleared by software. This is done by writing a one to its bit location.