Figure 1. CLKCTRL Block Diagram
The clock system consists of the Main Clock and other asynchronous clocks:
- Main Clock
This
clock is used by the CPU, RAM, Flash, the IO bus and all peripherals
connected to the IO bus. It is always running in Active and Idle sleep mode,
and can be running in Standby sleep mode if requested.
The main clock CLK_MAIN is prescaled and distributed by the Clock
Controller:
- CLK_CPU is used by
the CPU, SRAM and the NVMCTRL peripheral to access the non-volatile
memory
- CLK_PER is used by
all peripherals that are not listed under asynchronous clocks.
- Clocks running asynchronously to
the Main Clock domain:
- CLK_RTC is used by the
RTC/PIT. It will be requested when the RTC/PIT is enabled. The clock
source for CLK_RTC should only be changed if the peripheral is
disabled.
- CLK_WDT is used by the
WDT. It will be requested when the WDT is enabled.
- CLK_BOD is used by the
BOD. It will be requested when the BOD is enabled in Sampled Mode.
- CLK_TCD is used by the TCD. It will
be requested when the TCD is enabled. The clock source can only be
changed if the peripheral is disabled.
The clock source for the for the Main Clock domain is configured by writing
to the Clock Select bits (CLKSEL) in the Main Clock Control A register
(CLKCTRL.MCLKCTRLA). The asynchronous clock sources are configured by registers in the
respective peripheral.