In Normal mode, the system is single buffered in the transmit direction and
double buffered in the receive direction. This influences the data handling in the
following ways:
- 1.New bytes to be sent cannot be
written to the data register (SPI.DATA) before the entire transfer has completed. A
premature write will cause corruption of the transmitted data, and the hardware will
set the Write Collision Flag (INTFLAGS.WRCOL).
- 2.Received bytes are written to First
Receive Buffer Register immediately after the transmission is completed.
- 3.The First Receive Buffer Register has
to be read before the next transmission is completed or data will be lost. This
register is read by reading SPI.DATA.
- 4.The Transmit Buffer Register and
Second Receive Buffer Register are not used in Normal Mode.
After a transfer has completed, the Interrupt Flag (INTFLAGS.IF) will be set
in the Interrupt Flags Register (SPI.INTFLAGS). This will cause the corresponding interrupt
to be executed if this interrupt and the global interrupts are enabled. Setting the
Interrupt Enable (IE) bit in the Interrupt Control Register (SPI.INTCTRL) will enable the
interrupt.