System Configuration 0
Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRCSRC[1:0] | RESERVED | TOUTDIS | RSTPINCFG[1:0] | RESERVED | EESAVE | ||
AccessR | R | R | R | R | R | R | R |
Reset1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
CRC Source
Value | Name | Description |
---|---|---|
0x0 | FLASH | CRC of full Flash (boot, application code and application data) |
0x1 | BOOT | CRC of the boot section |
0x2 | BOOTAPP | CRC of application code and boot sections |
0x3 | NOCRC | No CRC |
Time Out Disable
When the TOUTDIS bit in FUSE.SYSCFG0 is ‘0
’ and
the RSTPINCFG bit field in FUSE.SYSCFG0 is configured to GPIO or RESET, there
will be a time out period after POR that blocks NVM writes.
The NVM Write Block will last for 768 OSC32K cycles after POR. The EEBUSY and
FBUSY bits in the NVMCTRL.STATUS register must read ‘0
’ before
the page buffer can be filled or NVM commands can be issued.
Value | Description |
---|---|
0 | NVM Write Block is enabled |
1 | NVM Write Block is disabled |
Reset Pin Configuration
Value | Description |
---|---|
0x0 | GPIO |
0x1 | UPDI |
0x2 | RESET |
Other | Reserved |
EEPROM Save during chip erase
Value | Description |
---|---|
0 | EEPROM erased during chip erase |
1 | EEPROM not erased under chip erase |