System Configuration 0

Name:
SYSCFG0
Offset:
0x05
Reset:
-
Access:
-
Bit76543210
CRCSRC[1:0]RESERVEDTOUTDISRSTPINCFG[1:0]RESERVEDEESAVE
AccessRRRRRRRR
Reset11110110

Bits 7:6 – CRCSRC[1:0]: CRC Source

CRC Source

See the CRC description for more information about the functionality.
ValueNameDescription
0x0 FLASH CRC of full Flash (boot, application code and application data)
0x1 BOOT CRC of the boot section
0x2 BOOTAPP CRC of application code and boot sections
0x3 NOCRC No CRC

Bit 5 – RESERVED

Bit 4 – TOUTDIS: Time Out Disable

Time Out Disable

This bit can disable the blocking of NVM writes after POR.

When the TOUTDIS bit in FUSE.SYSCFG0 is ‘0’ and the RSTPINCFG bit field in FUSE.SYSCFG0 is configured to GPIO or RESET, there will be a time out period after POR that blocks NVM writes.

The NVM Write Block will last for 768 OSC32K cycles after POR. The EEBUSY and FBUSY bits in the NVMCTRL.STATUS register must read ‘0’ before the page buffer can be filled or NVM commands can be issued.

Note: This fuse is not available for devices with 16 KB flash memory.
ValueDescription
0 NVM Write Block is enabled
1 NVM Write Block is disabled

Bits 3:2 – RSTPINCFG[1:0]: Reset Pin Configuration

Reset Pin Configuration

These bits select the Reset/UPDI pin configuration.
Note: When configuring the Reset Pin as GPIO, there is a potential conflict between the GPIO actively driving the output, and a 12V UPDI enable sequence initiation. To avoid this, the GPIO output driver is disabled for 768 OSC32K cycles after a System Reset. Enable any interrupts for this pin only after this period.
ValueDescription
0x0 GPIO
0x1 UPDI
0x2 RESET
Other Reserved

Bit 1 – RESERVED

Bit 0 – EESAVE: EEPROM Save during chip erase

EEPROM Save during chip erase

Note: If the device is locked, the EEPROM is always erased by a chip erase, regardless of this bit.
ValueDescription
0 EEPROM erased during chip erase
1 EEPROM not erased under chip erase