Timing of the First Interrupt
The PIT function
and the RTC function are running off the same counter inside the
prescaler, but both functions’ periods can be configured
independently:
- The RTC period is configured by
writing the PRESCALER bit field in RTC.CTRLA.
- The PIT period is configured by
writing the PERIOD bit field in RTC.PITCTRLA.
The prescaler is
OFF when both functions are OFF (RTC Enable bit (RTCEN) in RTC.CTRLA
and PIT Enable bit (PITEN) in RTC.PITCTRLA are zero), but it is
running (i.e. its internal counter is counting) when either function
is enabled.
For this reason, the timing of the first PIT interrupt output
is depending on whether the RTC function is already enabled or
not:
- When RTCEN in
RTC.CTRLA is zero and PITEN in RTC.PITCTRLA is written to
‘1’, the prescaler will start operating at the next edge of
CLK_RTC, counting from zero. The PIT interrupt output will
then toggle from ‘0’ to ‘1’ after a ½ period.
- When the RTC
function is already enabled (RTCEN is ‘1’), the prescaler is
already running. The timing of the first interrupt output
from the PIT depends on the value of the counter when the
prescaler is enabled. Since the application can’t access
that value, the first interrupt output may occur anytime
between writing PITEN to ‘1’ and up to a full PIT period
after.
Continuous
Operation
After the first interrupt output, the PIT will
continue toggling every ½ PIT period, resulting in a full PIT period
signal.
PIT Timing
Diagram for PERIOD=CYC16
For PERIOD=CYC16 in RTC.PITCTRLA, the PIT output effectively follows the
state of prescaler counter bit 3, so the resulting interrupt output has a period of
16 CLK_RTC cycles.
When both RTC and PIT functions are disabled, the
prescaler is OFF. The delay between writing PITEN to ‘1’ and the
first interrupt output is always ½ PIT period, with an
uncertainty of one leading CLK_RTC cycle.
When the RTC and hence the prescaler are already
enabled with any PRESCALER=DIVn, the time between writing PITEN
to ‘1’ and the first PIT interrupt can vary between virtually 0
and a full PIT period of 16 CLK_RTC cycles. The precise delay
between enabling the PIT and its first output is depending on
the prescaler’s counting phase: the depicted first interrupt in
the lower figure is produced by writing PITEN to ‘1’ at any time
inside the leading time window.
Figure 1. Timing Between PIT Enable and First Interrupt