Multi Slave Systems - SS Pin Functionality

The Slave Select (SS) pin plays a central role in the SPI configuration. Depending on the mode the part is running in and the configuration of this pin, it can be used to activate or deactivate the devices. The SS pin can be compared with a chip select pin that has some extra features.

In Master mode, the SS pin must be held high to ensure master SPI operation if this pin is configured as an input pin. A low level will switch the SPI into Slave mode and the hardware of the SPI will perform the following actions:

1.The master bit (MSTR) in the SPI Control Register (SPCR) is cleared and the SPI system becomes a slave. The direction of the pins will be switched according to Table 1.
2.The SPI Interrupt Flag (SPIF) in the SPI Status Register (SPSR) will be set. If the SPI interrupt and the global interrupts are enabled the interrupt routine will be executed.

This can be useful in systems with more than one master to avoid two masters accessing the SPI bus at the same time. If the SS pin is configured as output pin it can be used as a general purpose output pin, which does not affect the SPI system.

Note: In cases where the AVR is configured for Master mode and it can not be ensured that the SS pin will stay high between two transmissions, the status of the MSTR bit has to be checked before a new byte is written. After the MSTR bit has been cleared by a low level on the SS line, it must be set by the application to re-enable SPI Master mode.

In Slave mode the SS pin is always an input. When SS is held low, the SPI is activated and MISO becomes output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. The following table shows an overview of the SS Pin Functionality.

Table 1. Overview of the SS Pin Functionality
Mode	SS Configuration	SS Pin-level	Description
Slave	Always Input	High	Slave deactivated (deselected)
Slave	Always Input	Low	Slave activated (selected)
Master	Input	High	Master activated (selected)
	Input	Low	Master deactivated, switched to Slave mode
	Output	High	Master activated (selected)
	Output	Low	Master activated (selected)

Note: In Slave mode, the SPI logic will be Reset once the SS pin is brought high. If the SS pin is brought high during a transmission, the SPI will stop sending and receiving immediately and both data received and data sent must be considered as lost.

As shown in the preceding table , the SS pin in Slave mode is always an input pin. A low level activates the SPI of the device while a high level causes its deactivation. A Single Master Multiple Slave System with an AVR configured in Master mode and SS configured as output pin is shown in the following figure. The amount of slaves that can be connected to this AVR is only limited by the number of I/O pins to generate the slave select signals.

Figure 1. Multi Slave System

The ability to connect several devices to the same SPI bus is based on the fact that only one master and only one slave is active at the same time. The MISO, MOSI, and SCK lines of all the other slaves are tri-stated (configured as input pins of a high impedance with no pullup resistors enabled). A false implementation (for example, if two slaves are activated at the same time) can cause a driver contention which can lead to a CMOS latch-up state and must be avoided. Resistances of 1 to 10Ω in series with the pins of the SPI can be used to prevent the system from latching up. However this affects the maximum usable data rate, depending on the loading capacitance on the SPI pins.

Unidirectional SPI devices require just the clock line and one of the data lines. The device can use MISO line or the MOSI line depending on its purpose.