Data Direction Clear
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DIRCLR[7:0] | |||||||
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Data Direction Clear
Writing a '1' to DIRCLR[n] will clear the corresponding bit in PORT.DIR.
Reading this bit field will always return the value of PORT.DIR.