TMRx
Timer Low Byte Register
Name:
TMRx
Offset:
0xFCD,0xFC7,0xFC1
Reset:
Access:
Bit
15
14
13
12
11
10
9
8
TMRxH[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
TMRxL[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 15:8 – TMRxH[7:0]: Timer Most Significant Byte
Timer Most Significant Byte
Bits 7:0 – TMRxL[7:0]: Timer Least Significant Byte
Timer Least Significant Byte