An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage (VRST) on its positive edge, the delay counter starts the MCU after the Time-out period (tTOUT ) has expired. The External Reset can be disabled by the RSTDISBL fuse.
Figure 1. External Reset During
Operation