The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:
- One 8-bit output operand and one 8-bit result input
- Two 8-bit output operands and one 8-bit result input
- One 16-bit output operand and one 16-bit result input
Figure 1. AVR CPU General Purpose
Working Registers 
Note: A typical implementation of the AVR register file includes 32 general purpose
registers but ATtiny4/5/9/10 implement only 16 registers.
For reasons of compatibility the registers are numbered R16...R31, not
R0...R15.
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.