Sleep Mode Control Register

The Sleep Mode Control Register contains control bits for power management.

Name:
SMCR
Offset:
0x3A
Reset:
0x00
Access:
Bit76543210
SM[2:0]SE
AccessR/WR/WR/WR/W
Reset0000

Bits 3:1 – SM[2:0]: Sleep Mode Select

Sleep Mode Select

The SM[2:0] bits select between the five available sleep modes.

Table 1. Sleep Mode Select
SM[2:0] Sleep Mode
000 Idle
001 ADC Noise Reduction
010 Power-down
011 Reserved
100 Standby
101 Reserved
110 Reserved
111 Reserved
Note:
  1. This mode is available in all devices, although only ATtiny5/10 are equipped with an ADC

Bit 0 – SE: Sleep Enable

Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.