TIMSK0

Name:: TIMSK0
Offset:: 0x2B
Reset:: 0x00
Access:: -

Bit7	6	5	4	3	2	1	0
		ICIE0			OCIE0B	OCIE0A	TOIE0
Access		R/W			R/W	R/W	R/W
Reset		0			0	0	0

Bit 5 – ICIE0: Timer/Counter0, Input Capture Interrupt Enable

Timer/Counter0, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter0 Input Capture interrupt is enabled. The corresponding Interrupt Vector is executed when the ICF0 Flag, located in TIFR0, is set.

Bit 2 – OCIE0B: Timer/Counter0, Output Compare B Match Interrupt Enable

Timer/Counter0, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter 0 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF0B Flag, located in TIFR0, is set.

Bit 1 – OCIE0A: Timer/Counter0, Output Compare A Match Interrupt Enable

Timer/Counter0, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter0 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF0A Flag, located in TIFR0, is set.

Bit 0 – TOIE0: Timer/Counter0, Overflow Interrupt Enable

Timer/Counter0, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter0 Overflow interrupt is enabled. The corresponding Interrupt Vector is executed when the TOV0 Flag, located in TIFR0, is set.