Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRCBOOTDIS | CRCAPPDIS | RESERVED[1:0] | RSTPINCFG[1:0] | RESERVED | EESAVE | ||
AccessR | R | R | R | R | R | R | R |
Reset1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
CRC of Boot Section in Reset Disable
Value | Description |
---|---|
0 | Boot section undergoing a CRC before Reset releases |
1 | No CRC of the boot section before Reset releases |
CRC of Application Code Section in Reset Disable
Value | Description |
---|---|
0 | Application code section undergoing a CRC before Reset releases |
1 | No CRC of the application code section before Reset releases |
Reset Pin Configuration
Value | Description |
---|---|
0x0 | GPIO |
0x1 | RESET |
0x2 | UPDI |
0x3 |
For 24-pin device: UPDI, with external Reset on alternate location. Reserved for lower pin-counts. |
EEPROM Save during chip erase
Value | Description |
---|---|
0 | EEPROM erased during chip erase |
1 | EEPROM not erased under chip erase |