Control Register E Clear - Normal Mode
The individual status bit can be cleared by writing a one to its bit location. This allows each bit to be cleared without use of a read-modify-write operation on a single register.

Each Status bit can be read out either by reading TCA.CTRLESET or TCA.CTRLECLR.

Name:
CTRLECLR
Offset:
0x04
Reset:
0x00
Access:
-
Bit76543210
CMD[1:0]LUPDDIR
AccessR/WR/WR/WR/W
Reset0000

Bits 3:2 – CMD[1:0]: Command

Command

These bits are used for software control of update, restart, and reset of the timer/counter. The command bits are always read as zero.

ValueNameDescription
0x0 NONE No command
0x1 UPDATE Force update
0x2 RESTART Force restart
0x3 RESET Force hard Reset (ignored if TC is enabled)

Bit 1 – LUPD: Lock Update

Lock Update

Lock update can be used to ensure that all buffers are valid before an update is performed.

ValueDescription
0 The buffered registers are updated as soon as an UPDATE condition has occurred.
1 No update of the buffered registers is performed, even though an UPDATE condition has occurred.

Bit 0 – DIR: Counter Direction

Counter Direction

Normally this bit is controlled in hardware by the waveform generation mode or by event actions, but this bit can also be changed from software.

ValueDescription
0 The counter is counting up (incrementing).
1 The counter is counting down (decrementing).