Debouncing Action

Separate debouncers are embedded for each external input. The debouncer for each input is enabled/disabled with the Debounce Enable bits in the Tamper Control register (TAMPCTRL.DEBNCn). The debouncer configuration is fixed for all inputs as set by the Control B register (CTRLB).

The debouncing period duration is configurable using the Debounce Frequency field in the Control B register (CTRLB.DEBF). The period is set for all debouncers (i.e., the duration cannot be adjusted separately for each debouncer).

When TAMPCTRL.DEBNCn = 0, IN0n is detected asynchronously. See Figure 1 for an example.

When TAMPCTRL.DEBNCn = 1, the detection time depends on whether the debouncer operates synchronously or asynchronously, and whether majority detection is enabled or not. Refer the following table for more details.

Synchronous versus asynchronous stability debouncing is configured by the Debounce Asynchronous Enable bit in the Control B register (CTRLB.DEBASYNC):

• Synchronous (CTRLB.DEBASYNC = 0): IN0n is synchronized in two CLK_RTC periods and then must remain stable for four CLK_RTC_DEB periods before a valid detection occurs. See Figure 2 for an example.
• Asynchronous (CTRLB.DEBASYNC = 1): The first edge on IN0n is detected. Further detection is blanked until IN0n remains stable for four CLK_RTC_DEB periods. See Figure 3 for an example.

Majority debouncing is configured by the Debounce Majority Enable bit in the Control B register (CTRLB. CTRLB.DEBMAJ). IN0n must be valid for two out of three CLK_RTC_DEB periods. See Figure 4 for an example.