The connector area contains holes for two pin headers with 2x6 and 2x2 pins, to give access to several signals and device pins as shown in Table 1 and Table 2.
Pin headers with 2.54mm spacing or wires can be soldered in here. A connector for incircuit programming is mounted. Lastly the area contains cell balancing and a board ID system, which are described in more details in the next subsections.
Name | Description |
---|---|
PACK+ | Battery-pack positive input/output. Also connected to BATT pin. |
PACK- | Battery-pack negative input/output (ground). |
CELL+ | Cell stack positive terminal. |
CELL- | Cell stack negative terminal. |
VFET | VFET pin. |
VREG | Regulator output. Connected to VCC. |
PV1R | Cell1 positive input. |
PV2R | Cell2 positive input. |
PA0 | PA0 pin. |
PA1 | PA1 pin. |
PB0 | PB0 pin. |
PC0 | PC0 pin. Used for 1-wire SW-UART. Includes ESD protection. |
Name | Description |
---|---|
C1BO | Cell1 Balancing On input. |
C2BO | Cell2 Balancing On input. |
VREF | VREF. |
VGND | VREF ground. |
ISP programming via SPI interface. Table 2-3 shows connections. Alternative pin names are also noted.
Name | Pin no Description |
---|---|
MISO | 1 Serial data out. (PB3) |
VCC | 2 Supply voltage |
SCK | 3 Serial clock. (PB1) |
MOSI | 4 Serial data in. (PB2). |
RESET | 5 Reset signal (active low) |
GND | 6 Ground |