ADC - Analog-to-Digital Converter
SAMPDLY and ASDV Does Not Work Together With SAMPLEN
Pending Event Stuck When Disabling the ADC
ADC Functionality Cannot be Ensured with CLKADC Above 1.5 MHz and a Setting of 25% Duty Cycle
ADC Performance Degrades with CLKADC Above 1.5 MHz and VDD < 2.7V
ADC Interrupt Flags Cleared When Reading RESH
Changing ADC Control Bits During Free-Running Mode not Working
One Extra Measurement Performed After Disabling ADC Free-Running Mode
ADC Wake-Up with WCOMP
Parent topic:
Silicon Errata Issues