CPU / Bus Clocks

The CPU and AHB/APBx buses are clocked by the same physical clock source (referred in this module as the Main Clock). The CPU and bus clocks are divided into a number of clock domains. Each clock domain can run at different frequencies.

There are three clock domains:

Each clock domain (CPU, LP, BUP) can be changed on the fly. To ensure correct operation, frequencies must be selected so that BUPDIV ≥ LPDIV ≥ HSDIV. Also, frequencies must never exceed the specified maximum frequency for each clock domain. A module may be connected to several clock domains (for instance, AHB and APB).

The general main clock tree for the CPU and associated buses is shown in Figure 1.

Figure 1. CPU / Bus Clocks