Interrupts

Table 1. Available Interrupt Vectors and Sources For Devices With Up to 8 KB Flash
Offset Name Vector Description Conditions
0x00 Slave TWI Slave interrupt
  • DIF: Data Interrupt Flag in SSTATUS set
  • APIF: Address or Stop Interrupt Flag in SSTATUS set
0x02 Master TWI Master interrupt
  • RIF: Read Interrupt Flag in MSTATUS set
  • WIF: Write Interrupt Flag in MSTATUS set
Table 2. Available Interrupt Vectors and Sources For Devices With More Than 8 KB Flash
Offset Name Vector Description Conditions
0x00 Slave TWI Slave interrupt
  • DIF: Data Interrupt Flag in SSTATUS set
  • APIF: Address or Stop Interrupt Flag in SSTATUS set
0x04 Master TWI Master interrupt
  • RIF: Read Interrupt Flag in MSTATUS set
  • WIF: Write Interrupt Flag in MSTATUS set
When an interrupt condition occurs, the corresponding interrupt flag is set in the Master register (TWI.MSTATUS) or Slave Status register (TWI.SSTATUS).
When several interrupt request conditions are supported by an interrupt vector, the interrupt requests are ORed together into one combined interrupt request to the interrupt controller. The user must read the peripheral's INTFLAGS register to determine which of the interrupt conditions are present.