Control C - Master SPI Mode

This register description is valid only when the USART is in Master SPI mode (CMODE written to MSPI). For other CMODE values, see Control C - Async Mode.

See USART in Master SPI mode for a full description of the Master SPI mode operation.

Name:
CTRLC
Offset:
0x07
Reset:
0x00
Access:
-
Bit76543210
CMODE[1:0]UDORDUCPHA
AccessR/WR/WR/WR/W
Reset0000

Bits 7:6 – CMODE[1:0]: USART Communication Mode

USART Communication Mode

Writing these bits select the communication mode of the USART.

Writing a value different than 0x3 to these bits alters the available bit fields in this register, see Control C - Async Mode.

ValueNameDescription
0x0 ASYNCHRONOUS Asynchronous USART
0x1 SYNCHRONOUS Synchronous USART
0x2 IRCOM Infrared Communication
0x3 MSPI Master SPI

Bit 2 – UDORD: Data Order

Data Order

Writing this bit selects the frame format.

The receiver and transmitter use the same setting. Changing the setting of UDORD will corrupt all ongoing communication for both the receiver and the transmitter.

ValueDescription
0 MSB of the data word is transmitted first
1 LSB of the data word is transmitted first

Bit 1 – UCPHA: Clock Phase

Clock Phase

The UCPHA bit setting determines if data is sampled on the leading (first) edge or tailing (last) edge of XCKn. Refer to the Master SPI Mode Clock Generation for details.