Sample Control
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SAMPLEN[4:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | ||
Sample Length
These bits extend the ADC sampling length in a number of CLK_ADC cycles. By default, the sampling time is two CLK_ADC cycles. Increasing the sampling length allows sampling sources with higher impedance. The total conversion time increases with the selected sampling length.