A dual core device (e.g., dsPIC33CH DSCs) has a Master core and Slave core that can operate independently and can be programmed and debugged separately, during application development. Both processor (Master and Slave) subsystems have their own interrupt controllers, clock generators, ICD, port logic, I/O MUXes and PPS. The device is equivalent to having two complete dsPIC® DSCs on a single die.
Dual core devices have several modes of operation which correspond to different ways of creating and using projects:
Master Only Programming and Debugging
A dual core device is by default in Master Only mode; the Master Slave Interface (MSI) has the MSI1 Master Control Register (MSI1CON) Slave Enable bit (SLVEN) set to ‘0’.
A project for this device mode is no different from a project for any Microchip device. For details, see “Create a New Project.”
Slave Only Programming
For the slave project to work independently, the ports for the slave need to be assigned. Therefore a master project (e.g., MasterStub) is necessary that programs the master with the configuration bit settings (like which PORTS are assigned to slave). For details, see “Set Configuration Bits in the Configuration Bits Window.”
Two project are required for Slave Only Programming mode:
MasterStub must be programmed first and then SlaveOnly.
Slave Only Debugging
To debug the SlaveOnly project in the previous section, enable background debug
(S1DEBUG
) in the configuration settings:
// FS1ICD
#pragma config S1ICS = PGD2 // ICD Communication Channel Select bits
// (Communicate on PGEC2 and PGED2)
#pragma config S1DEBUG = ON // Background Debug (Enabled)
:
Master and Slave Programming and Debugging
In this mode, the Master project will be linked to the Slave project. That is, the Slave code resides in Master and Master must transfer the code to slave.
#include "Slav.h"
//The function to transfer the code from slave to master and start the slave is below.
_program_slave(1,0,Slav);
_start_slave();