Watchdog Timer Control Register
Name:
WDTCSR
Offset:
0x60 [ID-000004d0]
Reset:
0x00 / 0x08
Access:
-
Bit76543210
WDIFWDIEWDP [3] WDCEWDEWDP [2:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset0000x000

Bit 7 – WDIF: Watchdog Interrupt Flag

Watchdog Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

Bit 6 – WDIE: Watchdog Interrupt Enable

Watchdog Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode).

This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied.

Table 1. Watchdog Timer Configuration
WDTON(1) WDE WDIE Mode Action on Time-out
1 0 0 Stopped None
1 0 1 Interrupt Mode Interrupt
1 1 0 System Reset Mode Reset
1 1 1 Interrupt and System Reset Mode Interrupt, then go to System Reset Mode
0 X X System Reset Mode Reset
Note:
  1. WDTON Fuse set to '0' means programmed and '1' means unprogrammed.

Bit 5 – WDP [3] : Watchdog Timer Prescaler bit [3]

Watchdog Timer Prescaler bit [3]

Bit 4 – WDCE: Watchdog Change Enable

Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler bits, WDCE must be set.

Once written to '1', hardware will clear WDCE after four clock cycles.

Bit 3 – WDE: Watchdog System Reset Enable

Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure.

Bits 2:0 – WDP [2:0]: Watchdog Timer Prescaler

Watchdog Timer Prescaler

The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in the table below.

Table 2. Watchdog Timer Prescale Select
WDP[3:0] Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V
0000 2K (2048) cycles 16ms
0001 4K (4096) cycles 32ms
0010 8K (8192) cycles 64ms
0011 16K (16384) cycles 0.125s
0100 32K (32768) cycles 0.25s
0101 64K (65536) cycles 0.5s
0110 128K (131072) cycles 1.0s
0111 256K (262144) cycles 2.0s
1000 512K (524288) cycles 4.0s
1001 1024K (1048576) cycles 8.0s
1010 Reserved Reserved
1011 Reserved Reserved
1100 Reserved Reserved
1101 Reserved Reserved
1110 Reserved Reserved
1111 Reserved Reserved