Contents

Introduction Features Description Configuration Summary Ordering Information ATmega48PB ATmega88PB ATmega168PB Block Diagram Pin Configurations Pin Descriptions VCC GND Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port C (PC5:0) PC6/RESET Port D (PD7:0) Port E(PE3:0) AVCC AREF ADC7:6 (TQFP and VFQFN Package Only) I/O Multiplexing Comparison Between Processors Resources Data Retention About Code Examples Capacitive Touch Sensing QTouch Library AVR CPU Core Overview ALU – Arithmetic Logic Unit Status Register Status Register General Purpose Register File The X-register, Y-register, and Z-register Stack Pointer Stack Pointer Register Low and High byte Instruction Execution Timing Reset and Interrupt Handling Interrupt Response Time AVR Memories Overview In-System Reprogrammable Flash Program Memory SRAM Data Memory Data Memory Access Times EEPROM Data Memory EEPROM Read/Write Access Preventing EEPROM Corruption I/O Memory General Purpose I/O Registers Register Description Accessing 16-bit Registers EEPROM Address Register Low and High Byte EEPROM Data Register EEPROM Control Register GPIOR2 – General Purpose I/O Register 2 GPIOR1 – General Purpose I/O Register 1 GPIOR0 – General Purpose I/O Register 0 Unique Device ID SNOBRx - Serial Number Byte 8 to 0 System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clkCPU I/O Clock – clkI/O Flash Clock – clkFLASH Asynchronous Timer Clock – clkASY ADC Clock – clkADC Clock Sources Default Clock Source Clock Startup Sequence Clock Source Connections Low Power Crystal Oscillator Low Frequency Crystal Oscillator Calibrated Internal RC Oscillator 128kHz Internal Oscillator External Clock Clock Output Buffer Timer/Counter Oscillator System Clock Prescaler Register Description Oscillator Calibration Register Clock Prescaler Register Power Management and Sleep Modes Sleep Modes BOD Disable(1) Idle Mode ADC Noise Reduction Mode Power-down Mode Power-save Mode Standby Mode Extended Standby Mode Power Reduction Register Minimizing Power Consumption Analog to Digital Converter Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins On-chip Debug System Register Description Sleep Mode Control Register MCU Control Register Power Reduction Register System Control and Reset Resetting the AVR Reset Sources Power-on Reset External Reset Brown-out Detection Watchdog System Reset Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Watchdog Timer Overview Register Description MCU Status Register Watchdog Timer Control Register Interrupts Interrupt Vectors in ATmega48PB Interrupt Vectors in ATmega88PB Interrupt Vectors in ATmega168PB Register Description Moving Interrupts Between Application and Boot Space MCU Control Register External Interrupts Pin Change Interrupt Timing Register Description External Interrupt Control Register A External Interrupt Mask Register External Interrupt Flag Register Pin Change Interrupt Control Register Pin Change Interrupt Flag Register Pin Change Mask Register 2 Pin Change Mask Register 1 Pin Change Mask Register 0 I/O-Ports Overview Ports as General Digital I/O Configuring the Pin Toggling the Pin Switching Between Input and Output Reading the Pin Value Digital Input Enable and Sleep Modes Unconnected Pins Alternate Port Functions Alternate Functions of Port B Alternate Functions of Port C Alternate Functions of Port D Alternate Functions of Port E Register Description MCU Control Register Port B Data Register Port B Data Direction Register Port B Input Pins Address Port C Data Register Port C Data Direction Register Port C Input Pins Address Port D Data Register Port D Data Direction Register Port D Input Pins Address Port E Data Register Port E Data Direction Register Port E Input Pins Address 8-bit Timer/Counter0 with PWM Features Overview Definitions Registers Timer/Counter Clock Sources Counter Unit Output Compare Unit Force Output Compare Compare Match Blocking by TCNT0 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Timer/Counter Timing Diagrams Register Description TC0 Control Register A TC0 Control Register B TC0 Interrupt Mask Register General Timer/Counter Control Register TC0 Counter Value Register TC0 Output Compare Register A TC0 Output Compare Register B TC0 Interrupt Flag Register 16-bit Timer/Counter1 with PWM Features Overview Definitions Registers Accessing 16-bit Registers Reusing the Temporary High Byte Register Timer/Counter Clock Sources Counter Unit Input Capture Unit Input Capture Trigger Source Noise Canceler Using the Input Capture Unit Output Compare Units Force Output Compare Compare Match Blocking by TCNTn Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Phase and Frequency Correct PWM Mode Timer/Counter Timing Diagrams Register Description TC1 Control Register A TC1 Control Register B TC1 Control Register C TC1 Counter Value Low and High byte Input Capture Register 1 Low and High byte Output Compare Register 1 A Low and High byte Output Compare Register 1 B Low and High byte Timer/Counter 1 Interrupt Mask Register TC1 Interrupt Flag Register Timer/Counter0 and Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source Register Description General Timer/Counter Control Register 8-bit Timer/Counter2 with PWM and Asynchronous Operation Features Overview Definitions Registers Timer/Counter Clock Sources Counter Unit Output Compare Unit Force Output Compare Compare Match Blocking by TCNTn Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Timer/Counter Timing Diagrams Asynchronous Operation of Timer/Counter2 Timer/Counter Prescaler Register Description TC2 Control Register A TC2 Control Register B TC2 Counter Value Register TC2 Output Compare Register A TC2 Output Compare Register B TC2 Interrupt Mask Register TC2 Interrupt Flag Register Asynchronous Status Register General Timer/Counter Control Register SPI – Serial Peripheral Interface Features Overview SS Pin Functionality Slave Mode Master Mode Data Modes Register Description SPI Control Register 0 SPI Status Register 0 SPI Data Register 0 USART0 Features Overview Clock Generation Internal Clock Generation – The Baud Rate Generator Double Speed Operation (U2Xn) External Clock Synchronous Clock Operation Frame Formats Parity Bit Calculation USART Initialization Data Transmission – The USART Transmitter Sending Frames with 5 to 8 Data Bits Sending Frames with 9 Data Bit Transmitter Flags and Interrupts Parity Generator Disabling the Transmitter Data Reception – The USART Receiver Receiving Frames with 5 to 8 Data Bits Receiving Frames with 9 Data Bits Receive Compete Flag and Interrupt Receiver Error Flags Parity Checker Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception Asynchronous Clock Recovery Asynchronous Data Recovery Asynchronous Operational Range Start Frame Detection Multi-processor Communication Mode Using MPCMn Examples of Baud Rate Setting Register Description USART I/O Data Register 0 USART Control and Status Register 0 A USART Control and Status Register 0 B USART Control and Status Register 0 C USART Control and Status Register 0 D USART Baud Rate 0 Register Low and High byte USART in SPI Mode Features Overview Clock Generation SPI Data Modes and Timing Frame Formats USART MSPIM Initialization Data Transfer Transmitter and Receiver Flags and Interrupts Disabling the Transmitter or Receiver AVR USART MSPIM vs. AVR SPI Register Description 2-wire Serial Interface (I2C) Features 2-wire Serial Interface Bus Definition TWI Terminology Electrical Interconnection Data Transfer and Frame Format Transferring Bits START and STOP Conditions Address Packet Format Data Packet Format Combining Address and Data Packets into a Transmission Multi-master Bus Systems, Arbitration and Synchronization Overview of the TWI Module SCL and SDA Pins Bit Rate Generator Unit Bus Interface Unit Address Match Unit Control Unit Using the TWI Transmission Modes Master Transmitter Mode Master Receiver Mode Slave Receiver Mode Slave Transmitter Mode Miscellaneous States Combining Several TWI Modes Multi-master Systems and Arbitration Register Description TWI Bit Rate Register TWI Status Register TWI (Slave) Address Register TWI Data Register TWI Control Register TWI (Slave) Address Mask Register Analog Comparator Overview Analog Comparator Multiplexed Input Register Description ADC Control and Status Register B Analog Comparator Control and Status Register C Analog Comparator Control and Status Register Digital Input Disable Register 1 Analog-to-Digital Converter Features Overview Starting a Conversion Prescaling and Conversion Timing Changing Channel or Reference Selection ADC Input Channels ADC Voltage Reference ADC Noise Canceler Analog Input Circuitry Analog Noise Canceling Techniques ADC Accuracy Definitions ADC Conversion Result Temperature Measurement Register Description ADC Multiplexer Selection Register ADC Control and Status Register A ADC Data Register Low and High Byte (ADLAR=0) ADC Data Register Low and High Byte (ADLAR=1) ADC Control and Status Register B Digital Input Disable Register 0 debugWIRE On-chip Debug System Features Overview Physical Interface Software Break Points Limitations of debugWIRE Register Description debugWire Data Register Self-Programming the Flash, ATmega48PB Overview Performing Page Erase by SPM Filling the Temporary Buffer (Page Loading) Performing a Page Write Addressing the Flash During Self-Programming EEPROM Write Prevents Writing to SPMCSR Reading the Fuse and Lock Bits from Software Preventing Flash Corruption Programming Time for Flash when Using SPM Simple Assembly Code Example for a Boot Loader Register Description Store Program Memory Control and Status Register Boot Loader Support – Read-While-Write Self-Programming Features Overview Application and Boot Loader Flash Sections Application Section BLS – Boot Loader Section Read-While-Write and No Read-While-Write Flash Sections RWW – Read-While-Write Section NRWW – No Read-While-Write Section Boot Loader Lock Bits Entering the Boot Loader Program Addressing the Flash During Self-Programming Self-Programming the Flash Performing Page Erase by SPM Filling the Temporary Buffer (Page Loading) Performing a Page Write Using the SPM Interrupt Consideration While Updating BLS Prevent Reading the RWW Section During Self-Programming Setting the Boot Loader Lock Bits by SPM EEPROM Write Prevents Writing to SPMCSR Reading the Fuse and Lock Bits from Software Reading the Signature Row from Software Preventing Flash Corruption Programming Time for Flash when Using SPM Simple Assembly Code Example for a Boot Loader ATmega88PB Boot Loader Parameters ATmega168PB Boot Loader Parameters Register Description SPMCSR – Store Program Memory Control and Status Register Memory Programming Program And Data Memory Lock Bits Fuse Bits Latching of Fuses Signature Bytes Calibration Byte Page Size Parallel Programming Parameters, Pin Mapping, and Commands Signal Names Parallel Programming Enter Programming Mode Considerations for Efficient Programming Chip Erase Programming the Flash Programming the EEPROM Reading the Flash Reading the EEPROM Programming the Fuse Low Bits Programming the Fuse High Bits Programming the Extended Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Reading the Calibration Byte Parallel Programming Characteristics Serial Downloading Serial Programming Pin Mapping Serial Programming Algorithm Serial Programming Instruction set SPI Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics ATmega48PB/88PB DC Characteristics ATmega168PB DC Characteristics Speed Grades Clock Characteristics Calibrated Internal RC Oscillator Accuracy External Clock Drive Waveforms External Clock Drive System and Reset Characteristics SPI Timing Characteristics Two-wire Serial Interface Characteristics ADC Characteristics Parallel Programming Characteristics Typical Characteristics ATmega48PB/88PB Typical Characteristics Active Supply Current Idle Supply Current ATmega48PB/88PB Supply Current of IO Modules Example Power-down Supply Current Power-save Supply Current Power-standby Supply Current Pin Pull-Up Pin Driver Strength Pin Threshold and Hysteresis BOD Threshold Internal Oscillator Speed Current Consumption of Peripheral Units Current Consumption in Reset and Reset Pulse width ATmega168PB Typical Characteristics Active Supply Current Idle Supply Current ATmega168PB Supply Current of IO Modules Example Power-down Supply Current Power-save Supply Current Power-Standby Supply Current Pin Pull-Up Pin Driver Strength Pin Threshold and Hysteresis BOD Threshold Internal Oscillator Speed Current Consumption of Peripheral Units Current Consumption in Reset and Reset Pulse width Register Summary Instruction Set Summary Packaging Information 32A 32MS1 Errata Errata ATmega48PB Rev. A Rev. B Rev. C Rev. D to J Rev. K Errata ATmega88PB Rev. A Rev. B Rev. C Rev. D to J Rev. K Errata ATmega168PB Rev. A Rev. B Rev. C Rev. D to M Rev. N to O Datasheet Revision History Rev. DS40001909A – 05/2017 Rev. 42176G – 03/2016 Rev. 42176F – 02/2016 Rev. 42176E – 10/2015 Rev. 42176D – 04/2015 Rev. 42176C – 03/2015 Rev. 42176B – 11/2014 Rev. 42176A - 11/2014 Legal Disclaimer The Microchip Web Site Customer Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service