To ensure that masters with latency requirements get sufficient priority when accessing RAM, priority levels can be assigned to the masters for different types of access.
The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any access to the RAM, the RAM also receives the QoS level. The QoS levels and their corresponding bit values for the QoS level configuration is shown in the table below.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Background (no sensitive operation) |
| 0x1 | LOW | Sensitive Bandwidth |
| 0x2 | MEDIUM | Sensitive Latency |
| 0x3 | HIGH | Critical Latency |
If a master is configured with QoS level DISABLE (0x0) or LOW (0x1) there will be a minimum latency of one cycle for the RAM access.
The priority order for concurrent accesses are decided by two factors. First, the QoS level for the master and second, a static priority given by the port ID. The lowest port ID has the highest static priority. See the tables below for details.
The MTB has a fixed QoS level HIGH (0x3).
The CPU QoS level can be written/read, using 32-bit access only, at address 0x4100C114, bits [1:0]. Its reset value is 0x3.
Refer to different master QOSCTRL registers for configuring QoS for the other masters (USB, DMAC).
| SRAM Port Connection | Port ID | Connection Type | QoS | default QoS |
|---|---|---|---|---|
| CM0+ - Cortex M0+ Processor | 0 | Bus Matrix | 0x4100C114, bits[1:0](1) | 0x3 |
| DSU - Device Service Unit | 1 | Bus Matrix | 0x4100201C, bits[1:0](1) | 0x2 |
| DMAC - Direct Memory Access Controller - Data Access | 2 | Bus Matrix | IP-QOSCTRL.DQOS | 0x2 |
| DMAC - Direct Memory Access Controller - Fetch Access | 3, 4 | Direct | IP-QOSCTRL.FQOS | 0x2 |
| DMAC - Direct Memory Access Controller - Write-Back Access | 5, 6 | Direct | IP-QOSCTRL.WRBQOS | 0x2 |
| USB - Universal Serial Bus | 7 | Direct | IP-QOSCTRL | 0x3 |
| MTB - Micro Trace Buffer | 8 | Direct | STATIC-3 | 0x3 |