External interrupt
signals connect to the NVIC, and the NVIC prioritizes the interrupts.
Software can set the priority of each interrupt. The NVIC and the
Cortex-M0+ processor core are closely coupled, providing low latency
interrupt processing and efficient processing of late arriving
interrupts. Refer to NVIC-Nested Vector Interrupt Controller and the Cortex-M0+ Technical Reference Manual for
details (http://www.arm.com).Note: When the CPU
frequency is much higher than the APB frequency it is recommended to
insert a memory read barrier after each CPU write to registers
mapped on the APB. Failing to do so in such conditions may lead to
unexpected behavior such as e.g. re-entering a peripheral interrupt
handler just after leaving it.